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Where the use of VHDL-2008’s “var” is not required?
As for 2009, VHDL-2008 has introduced the “var” type to let a parameter to be optional.
I know that the “var” is a new feature, but if I use the “var” to replace an integer, will it be meaningless?
For instance:
type clk_state is (reset, clk, hold);
constant clk: time:=’1ns’; — timer clock
signal clk_signal: clk_state := hold;
A:
I think that’s not true, since the param might not be used: you can choose to define the signal as clk_state
A:
What I like about var is its flexibility. If you want a signal to be optional, now you can just add the var type without a type casting, thus allowing the signal to be of mixed types. A classic example would be generating a clock with a clock rate constant, and then the clock rate is created with a switch statement and then a var definition.
process(clk_sig)
begin
if clk_sig.rate = time_domain_clock_event then
— Clock timed
else
— Clock with no rate
— switch statements can be put inside processes if needed
— instead of a constant
end if;
end process;
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